mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 520
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Version 1 ColdFire Debug (CF1_DEBUG)
22.3.10.1 Resulting Set of Possible Trigger Combinations
The resulting set of possible breakpoint trigger combinations consists of the following options where ||
denotes logical OR, && denotes logical AND, and {} denotes an optional additional trigger term:
One-level triggers of the form:
if
if
if
Two-level triggers of the form:
if
if
In these examples, PC_breakpoint is the logical summation of the PBR0/PBMR, PBR1, PBR2, and PBR3
breakpoint registers; Address_breakpoint is a function of ABHR, ABLR, and AATR; Data_breakpoint is
a function of DBR and DBMR. In all cases, the data breakpoints can be included with an address
breakpoint to further qualify a trigger event as an option.
The breakpoint registers can also be used to define the start and stop recording conditions for the PST trace
buffer. For information on this functionality, see
(CSR2)”.
22.3.11 PST Buffer (PSTB)
The PST trace buffer contains 64 six-bit entries, packed consecutively into 12 longword locations. See
Figure 22-16
The write pointer for the trace buffer is available as CSR2[PSTBWA]. Using this pointer, it is possible to
determine the oldest-to-newest entries in the trace buffer.
22-28
(PC_breakpoint)
(PC_breakpoint || Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint {&& Data_breakpoint})
(PC_breakpoint)
then if (Address_breakpoint{&& Data_breakpoint})
(Address_breakpoint {&& Data_breakpoint})
then if (PC_breakpoint)
for an illustration of how the buffer entries are packed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 22-22. Access Size and Operand Data Location
Address[1
00
01
10
11
0x
1x
xx
–
0]
Access Size
Longword
Section 22.3.3, “Configuration/Status Register 2
Word
Word
Byte
Byte
Byte
Byte
Operand Location
D[31
D[23
D[31
D[15
D[15
D[31
D[7
–
–
–
–
–
–
–
24]
16]
0]
16]
8]
0]
0]
Freescale Semiconductor
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