mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 263
mcf51ac256a
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mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF51AC256A.pdf
(566 pages)
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The
11.4.14 Fault control mode
The fault control mode is enabled if (FTMEN = 1) and (FAULTM[1:0] not = 00).
First the fault input signal is synchronized by the system clock (synchronizer block in
Following synchronization, the fault input signal enters the filter block. When there is a state change in the
fault input signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable on the
fault input, the counter continues to increment. If the 5-bit counter overflows (the counter exceeds the
value of the FFVAL[3:0] bits), the new fault input value is validated. It is then transmitted as a pulse edge
to the edge detector.
Freescale Semiconductor
Table 11-24
channel (n) output
(before output mask)
channel (n) output
(after output mask)
CHnOM bit
Output mask is only available when (FTMEN = 1) and (COMBINE = 1) and
(CPWMS = 0). Output mask with (FTMEN = 0) or (COMBINE = 0) or
(CPWMS = 1) is not recommended and its results are not guaranteed.
FTM counter
Table 11-24. Output mask result for channel (n) (before the polarity control)
shows the output mask result before the polarity control.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
CHnOM bit
0
1
Figure 11-75. Output mask
the beginning of new PWM cycles
Output mask input
to be available in the channel (n) output
inactive state
inactive state
active state
active state
configured PWM signal starts
NOTE
Output mask result
inactive state
inactive state
active state
channel (n) output is disabled
FlexTimer Module (FTMV1)
Figure
11-76).
11-63
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