mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 386

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Multipurpose Clock Generator (MCGV3)
To change from FEI clock mode to FBI clock mode, follow this procedure:
16-18
5. Write to the MCGC4 register to determine the DCO output (MCGOUT) frequency range. Make
6. Wait for the LOCK bit in MCGSC to become set, indicating that the FLL has locked to the new
1. Change the CLKS bits in MCGC1 to %01 so that the internal reference clock is selected as the
2. Wait for the CLKST bits in the MCGSC register to change to %01, indicating that the internal
— If in FEE mode, check to make sure the IREFST bit is cleared and the LOCK bit is set before
— If in FBE mode, check to make sure the IREFST bit is cleared, the LOCK bit is set, and the
sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
— By default, with DMX32 cleared to 0, the FLL multiplier for the DCO output is 512. For greater
— When using a 32.768 kHz external reference, if the maximum low-range DCO frequency that
— When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that
— When using a 32.768 kHz external reference, if the maximum high-range DCO frequency that
multiplier value designated by the DRS and DMX32 bits.
system clock source.
reference clock has been appropriately selected.
external clock source has finished its initialization cycles and stabilized. Typical crystal startup
times are given in Appendix A, “Electrical Characteristics”.
moving on.
CLKST bits have changed to %10 indicating the external reference clock has been
appropriately selected. Although the FLL is bypassed in FBE mode, it is still on and will lock
in FBE mode.
flexibility, if a mid-range FLL multiplier of 1024 is desired instead, set the DRS[1:0] bits to
%01 for a DCO output frequency of 33.55 MHz. If a high-range FLL multiplier of 1536 is
desired instead, set the DRS[1:0] bits to %10 for a DCO output frequency of 50.33 MHz.
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %00 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 608 will be 19.92 MHz.
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %01 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1216 will be 39.85 MHz.
can be achieved with a 32.768 kHz reference is desired, set the DRS[1:0] bits to %10 and set
the DMX32 bit to 1. The resulting DCO output (MCGOUT) frequency with the new multiplier
of 1824 will be 59.77 MHz.
Setting DIV32 (bit 4) in MCGC3 is strongly recommended for FLL external
modes when using a high frequency range (RANGE = 1) external reference
clock. The DIV32 bit is ignored in all other modes.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
NOTE
Freescale Semiconductor