mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 523

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

If the VBus is enabled, the assertion of the BKPT input is treated as a pseudo-interrupt; asserting BKPT
creates a pending halt postponed until the processor core samples for halts/interrupts. The processor
samples for these conditions once during the execution of each instruction. If a pending halt is detected,
the processor suspends execution and enters the halted state. The behavior of the BKPT input pin is
equivalent to receiving a BACKGROUND command via the 1-pin BDM interface.
The processor’s run/stop/halt status is always accessible in XCSR[CPUHALT,CPUSTOP]. Additionally,
CSR[27–24] indicate the halt source, showing the highest priority source for multiple halt conditions. This
field is cleared by a read of the CSR. A processor halt due to the PSTB full condition as indicated by
CSR2[PSTH] is also reflected in CSR[BKPT]. The debug GO command clears CSR[26–24] and
CSR2[PSTBH].
Freescale Semiconductor
PSTB full condition
after reset negated
for ≥2 bus clocks
for POR or BDM
BACKGROUND
BKGD held low
Halt Source
command
reset
Halt Timing
Immediate
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Pending
Pending
BDM enabled and
BDM disabled or
Flash unsecure
flash unsecure
Table 22-23. CPU Halt Sources (continued)
Flash secure
flash secure
PSTB
Illegal command response and BACKGROUND command is ignored.
PSTB obtrusive recording mode pends halt in the processor if the trace
buffer reaches its full threshold (full is defined as before the buffer is
overwritten). When a pending condition is asserted, the processor halts
at the next sample point.
Enters debug mode with XCSR[ENBDM, CLKSW] set. The full set of
BDM commands is available and debug can proceed.
If the core is reset into a debug halt condition, the processor’s response
to the GO command depends on the BDM command(s) performed while
it was halted. Specifically, if the PC register was loaded, the GO
command causes the processor to exit halted state and pass control to
the instruction address in the PC, bypassing normal reset exception
processing. If the PC was not loaded, the GO command causes the
processor to exit halted state and continue reset exception processing.
Enters debug mode with XCSR[ENBDM, CLKSW] set. The allowable
commands are limited to the always-available group. A GO command to
start the processor is not allowed. The only recovery actions in this mode
are:
• Issue a BDM reset setting CSR2[BDFR] with CSR2[BDHBR] cleared
• Erase the flash to unsecure the memory and then proceed with debug
• Power cycle the device with the BKGD pin held high to reset into the
Processor is
Processor is
and the BKGD pin held high to reset into normal operating mode
normal operating mode
stopped
running
Halt is made pending in the processor. The processor
samples for pending halt and interrupt conditions
once per instruction. When a pending condition is
asserted, the processor halts execution at the next
sample point.
Processing of the BACKGROUND command is
treated in a special manner. The processor exits the
stopped mode and enters the halted state, at which
point all BDM commands may be exercised. When
restarted, the processor continues by executing the
next sequential instruction (the instruction following
STOP).
Description
Version 1 ColdFire Debug (CF1_DEBUG)
22-31