mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 488

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
When either half of the 16-bit capture register is read, the other half is latched into a buffer to support
coherent 16-bit accesses in big-endian or little-endian order. The coherency sequence can be manually
reset by writing to TPMxCnSC.
An input capture event sets a flag bit (CHnF) that optionally generates a CPU interrupt request.
While in BDM, the input capture function works as configured. When an external event occurs, the TPM
latches the contents of the TPM counter (frozen because of the BDM mode) into the channel value registers
and sets the flag bit.
21.4.2.2
With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in TPMxCnVH:TPMxCnVL
registers of an output compare channel, the TPM can set, clear, or toggle the channel pin.
Writes to any of TPMxCnVH and TPMxCnVL registers actually write to buffer registers. In output
compare mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their write buffer
only after both bytes were written and according to the value of CLKSB:CLKSA bits:
The coherency sequence can be manually reset by writing to the channel status/control register
(TPMxCnSC).
An output compare event sets a flag bit (CHnF) that optionally generates a CPU interrupt request.
21.4.2.3
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the value of the modulus register
(TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the value of the timer channel
register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by ELSnA bit. 0% and
100% duty cycle cases are possible.
The time between the modulus overflow and the channel match value (TPMxCnVH:TPMxCnVL) is the
pulse width or duty cycle
high, and the channel match forces the PWM signal low. If ELSnA is set, the counter overflow forces the
PWM signal low, and the channel match forces the PWM signal high.
21-16
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If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
If CLKSB and CLKSA are not cleared, the registers are updated at the next change of the TPM
counter (end of the prescaler counting) after the second byte is written.
Output Compare Mode
Edge-Aligned PWM Mode
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(Figure
21-14). If ELSnA is cleared, the counter overflow forces the PWM signal
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