mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 458

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16-Bit Serial Peripheral Interface (SPI16)
20.4.3
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear.
In slave mode, SPSCK is the SPI clock input from the master.
In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is
determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2.
be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle
state.
is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data
output pin. Also, if the slave is not selected (SS is high), then the SPSCK input is ignored and no internal
shifting of the SPI shift register takes place.
Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI
data in a slave mode. For these simpler devices, there is no serial data out pin.
As long as no more than one slave device drives the system slave’s serial data output line, it is possible for
several slaves to receive the same transmission from a master, although the master would not receive return
information from all of the receiving slaves.
If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SPSCK input cause the data
at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the serial data input pin
to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift
into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA
is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data
output pin. After the eighth (SPIMODE = 0) or sixteenth (SPIMODE = 1) shift, the transfer is considered
complete and the received data is transferred into the SPI data registers. To indicate transfer is complete,
the SPRF flag in the SPI Status Register is set.
20-18
The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin
The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must
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SPSCK
MISO, MOSI pin
SS pin
Slave Mode
When peripherals with duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the same
system slave’s serial data output line.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
NOTE
Freescale Semiconductor