mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 42

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Modes of Operation
3.7.3
Stop4 mode is entered by executing a STOP instruction under the conditions shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. Stop4 can
be exited by asserting RESET, or by an interrupt from one of the following sources: RTI, MSCAN wakeup
interrupt, SCI edge detect interrupt, LVD, ADC, IRQ, KBI, or ACMP. If stop4 is exited by means of the
RESET pin, then the MCU is reset and operation will resume after processing the reset exception. Exit by
means of one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector.
3.7.3.1
The LVD is capable of generating either an interrupt or a reset when the supply voltage drops below the
LVD voltage. If the LVD is enabled in stop (SPMSC1[LVDE] && SPMSC1[LVDSE] = 1) at the time the
CPU executes a STOP instruction, then the voltage regulator remains active during stop mode. If the user
attempts to enter stop2 mode with the LVD enabled for stop mode, the MCU enters stop4 mode instead.
For the ADC to operate, the LVD must be left enabled when entering stop4 mode. For the ACMP to operate
when ACMPSC[ACGBS] is set, the LVD must be left enabled when entering stop4. For the OSC to
operate with an external reference when MCGC2[RANGE] is set, the LVD must be left enabled when
entering stop4 mode.
3.8
When the MCU enters any stop mode (WAIT not included), system clocks to the internal peripheral
modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug
logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer
to
behavior in stop modes.
When the MCU enters wait mode, system clocks to the internal peripheral modules continue based on the
settings of the clock gating control registers (SCGC1 and SCGC2).
Table 3-2
low power modes.
3-6
Section 3.7.1, “Stop2 Mode,”
On-Chip Peripheral Modules in Stop and Wait Modes
defines terms used in
Stop4 Mode
LVD Enabled in Stop Mode
Voltage Regulator
The interrupt source must not be masked by software if it is active and
enabled in stop3 or stop4. Failure to do so may lead to a high current
condition with the CPU remaining in stop mode.
Full Regulation
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 3-3
Table 3-2. Abbreviations used in
and
Section 3.7.2, “Stop3 Mode,”
to describe operation of components on the chip in the various
Clocked
NOTE
FullOn
1
Table 3-3
for specific information on system
Not Clocked
FullADACK
FullNoClk
Freescale Semiconductor
2
Table
3-1. The