mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 512

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Version 1 ColdFire Debug (CF1_DEBUG)
development system. BAAR is loaded any time AATR is written and is initialized to a value of 0x05,
setting supervisor data as the default address space. The upper 24 bits of this register are reserved for future
use and any attempted write of these bits is ignored.
22.3.6
AATR defines address attributes and a mask to be matched in the trigger. The register value is compared
with address attribute signals from the processor’s high-speed local bus, as defined by the setting of the
trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06
using the WDEBUG instruction and through the BDM port using the WRITE_DREG command.
22-20
Field
31–8
6–5
4–3
2–0
TM
SZ
TT
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
7
DRc: 0x06 (AATR)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
DRc: 0x05 (BAAR)
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM SZM
R
W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
R
Reserved for future use by the debug module, must be cleared.
Read/Write.
0 Write
1 Read
Size.
00 Longword
01 Byte
10 Word
11 Reserved
Transfer type. See the TT definition in the AATR description,
(AATR)”.
Transfer modifier. See the TM definition in the AATR description,
(AATR)”.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Address Attribute Trigger Register (AATR)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-9. Address Attribute Trigger Register (AATR)
Figure 22-8. BDM Address Attribute Register (BAAR)
Table 22-12. BAAR Field Descriptions
Description
0
14
0
Section 22.3.6, “Address Attribute Trigger Register
13
0
Section 22.3.6, “Address Attribute Trigger Register
12
0
TTM
11
0
10
0
TMM
0
9
9
8
0
Access: Supervisor write-only
8
Access: Supervisor write-only
R
0
7
7
0
6
6
Freescale Semiconductor
SZ
SZ
5
0
5
4
BDM write-only
0
4
TT
TT
BDM write-only
3
0
3
2
1
2
TM
1
TM
0
1
0
1
0

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