mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 455

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

20.3.8
The SPI Clear Interrupt register has 4 bits dedicated for clearing the interrupts. Writing 1 to these bits clears
the respective interrupts if INTCLR bit in SPIxCR3 is set.
It also have 2 bits to indicate the transmit fifo and receive fifo overrun conditions. When receive fifo is full
and a data is received RXFOF flag is set. Similarily when transmit fifo is full and write happens to SPIDR
TXFOF is set. These flags gets cleared when a read happens to this register with the flags set.
There are two more bits to indicate the error flags. These flags gets set when due to some spurious reasons
entries in fifo becomes greater than 8. At this point all the flags in status register gets reset and entries in
FIFO are flushed with respective error flags set. These flags are cleared when a read happen at SPIxCI with
the error flags set.
Note: Bits [7:4] are readonly bits. These bits gets cleared when a read happens to this register with the flags set. Bits [3:0] are
Freescale Semiconductor
RNFULLIEN
FIFOMODE
TNEARIEN
INTCLR
Reset
Field
clear interrupts bits which clears the interrupts by writing 1 to respective bits. Reading these bits always return 0.
3
2
1
0
W
R
TXFERR
SPI Clear Interrupt Register (SPIxCI)
Interrupt Clearing Mechanism Select - This bit selects the mechanism by which SPRF, SPTEF, TNEAREF,
RNFULLF interrupts gets cleared.
0 Interrupts gets cleared when respective flags gets cleared depending on the state of FIFOs
1 Interrupts gets cleared by writing to the SPIxCI respective bits.
Transmit FIFO Nearly Empty Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when
the TNEAREF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPTIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0.
0 No interrupt on Transmit FIFO Nearly Empty Flag being set.
1 Enable interrupts on Transmit FIFO Nearly Empty Flag being set.
Receive FIFO Nearly Full Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when the
RNEARFF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE = 0.
0 No interrupt on RNEARFF being set.
1 Enable interrupts on RNEARFF being set.
SPI FIFO Mode Enable — This bit enables the SPI to utilise a 64-bit FIFO (8bytes 4 16-bit words) for both
transmit and receive buffers.
0 Buffer mode disabled.
1 Data available in the receive data buffer.
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
RXFERR
0
6
Table 20-9. SPIxC3 Register Field Descriptions
TXFOF
0
5
RXFOF
0
4
Description
TNEAREFCI RNFULLFCI
3
0
16-Bit Serial Peripheral Interface (SPI16)
0
2
SPTEFCI
0
1
SPRFCI
0
0
20-15