mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 198

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Cyclic Redundancy Check Generator (CRCV2)
10.4
To enable the CRC function, a write to the CRCH register will trigger the first half of the seed mechanism
which will place the CRCH value directly into bits 15-8 of the CRC generator shift register. The CRC
generator will then expect a write to CRCL to complete the seed mechanism.
As soon as the CRCL register is written to, its value will be loaded directly into bits 7-0 of the shift register,
and the second half of the seed mechanism will be complete. This value in CRCH:CRCL will be the initial
seed value in the CRC generator.
Now the first byte of the data on which the CRC calculation will be applied must be written to CRCL. This
write after the completion of the seed mechanism will trigger the CRC module to begin the CRC checking
process. The CRC generator will shift the bits in the CRCL register (MSB first) into the shift register of
the generator. After all 8 bits have been shifted into the CRC generator (in the next bus cycle after the data
write to CRCL), the result of the shifting, or the value currently in the shift register, can be read directly
from CRCH:CRCL, and the next data byte to include in the CRC calculation can be written to the CRCL
register.
This next byte will then also be shifted through the CRC generator’s 16-bit shift register, and after the
shifting has been completed, the result of this second calculation can be read directly from CRCH:CRCL.
After each byte has finished shifting, a new CRC result will appear in CRCH:CRCL, and an additional
byte may be written to the CRCL register to be included within the CRC16-CCITT calculation. A new
CRC result will appear in CRCH:CRCL each time 8-bits have been shifted into the shift register.
To start a new CRC calculation, write to CRCH, and the seed mechanism for a new CRC calculation will
begin again.
10.4.1
The CRC polynomial 0x1021 (x
proposed by the ITU-T (formerly CCITT) committee.
Although the ITU-T recommendations are very clear about the polynomial to be used, 0x1021, they accept
variations in the way the polynomial is implemented:
10-4
CRCL
Field
7–0
•
•
ITU-T V.41 implements the same circuit shown in
0x0000.
ITU-T T.30 and ITU-T X.25 implement the same circuit shown in
recommend the final CRC result to be negated (one-complement operation). Also, they
recommend a SEED = 0xFFFF.
CRCL — This is the low byte of the 16-bit CRC register. Normally, a write to CRCL will cause the CRC generator to
begin clocking through the 16-bit CRC generator. As a special case, if a write to CRCH has occurred previously, a
subsequent write to CRCL will load the value in the register as the low byte of a 16-bit seed value directly into bits
7–0 of the shift register in the CRC generator. A read of CRCL will read bits 7–0 of the current CRC calculation result
directly out of the shift register in the CRC generator.
Functional Description
ITU-T (CCITT) Recommendations and Expected CRC Results
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
16
Table 10-3. Register Field Descriptions
+ x
12
+ x
5
+ 1) is popularly known as CRC-CCITT since it was initially
Description
Figure
10-1, but it recommends a SEED =
Figure
10-1, but they
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