mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 542

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
monitoring as the execution of this command is considerably less obtrusive to the real-time operation of
an application than a BACKGROUND/read-PC/GO command sequence.
22.4.1.5.18 WRITE_CREG
If the processor is halted, this command writes the 32-bit operand to the selected control register. This
register grouping includes the PC, SR, CPUCR, VBR, and OTHER_A7. Accesses to processor control
registers are always 32-bits wide, regardless of implemented register width. The register is addressed
through the core register number (CRN). See
If the processor is not halted, this command is rejected as an illegal operation and no operation is
performed.
22.4.1.5.19 WRITE_DREG
This command writes the 32-bit operand to the selected debug control register. This grouping includes all
the debug control registers ({X}CSRn, BAAR, AATR, TDR, PBRn, PBMR, ABxR, DBR, DBMR).
Accesses to debug control registers are always 32-bits wide, regardless of implemented register width. The
register is addressed through the core register number (CRN). See
22-50
When writing XCSR, CSR2, or CSR3, WRITE_DREG only writes
bits 23–0. The upper byte of these debug registers is only written with the
special WRITE_XCSR_BYTE, WRITE_CSR2_BYTE, and
WRITE_CSR3_BYTE commands.
Write CPU control register
Write debug control register
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
0xC0+CRN
0x80+CRN
host →
host →
target
target
CREG data
DREG data
[31–24]
[31–24]
host →
host →
target
target
Table 22-24
CREG data
DREG data
NOTE
[23–16]
[23–16]
host →
host →
target
target
for the CRN details when CRG is 11.
CREG data
DREG data
host →
host →
[15–8]
[15–8]
target
target
Table 22-4
Active Background
DREG data
CREG data
host →
host →
target
target
Non-intrusive
[7–0]
[7–0]
for CRN details.
D
Y
D
Y
L
L
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