mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 216

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
11.3.9
FTMxSTATUS contains a copy of the status flag CHnF bit (in FTMxCnSC register) for each FTM channel
for simpler software driver.
11.3.10 FTM Features Mode Selection Register (FTMxMODE)
This read/write register contains the control bits used to configure the fault interrupt and fault control
mode, write protection, channel output initialization and enable the enhanced features of the FTM. These
controls relate to all channels within this module.
11-16
Reset
CHnF
Field
7-0
W
R
CH7F
Channel (n) flag. When channel (n) is an input-capture channel, this read/write bit is set when an active edge
occurs on the channel (n) pin. When channel (n) is an output compare or edge-aligned/center-aligned PWM
channel, CHnF is set when the value in the FTM counter registers matches the value in the FTM channel (n) value
registers. When channel (n) is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or
100%, CHnF will not be set even when the value in the FTM counter registers matches the value in the FTM
channel (n) value registers. When channel (n) is in combine mode, CHnF is always set when the value in the FTM
counter matches the value in the FTM channel (n) value.
Clear CHnF by reading FTMxSTATUS while CHnF is set and then writing a logic 0 to the selected CHnF. If another
request to set the CHnF bit occurs before the clearing sequence is complete, the sequence is reset so CHnF
remains set after the clear sequence is completed for the earlier CHnF.
Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or match event occurred on channel (n)
1 Input capture or match event on channel (n)
Note: Each CHnF bit in FTMxSTATUS register is a copy of CHnF bit in FTMxCnSC register. All CHnF bits can be
FTM Capture and Compare Status Register (FTMxSTATUS)
0
0
7
The use of FTMxSTATUS register is only available when (FTMEN = 1) and
(COMBINE = 1) and (CPWMS = 0). The use of this register with (FTMEN
= 0) or (COMBINE = 0) or (CPWMS = 1) is not recommended and its
results are not guaranteed.
Figure 11-12. FTM Capture and Compare Status Register (FTMxSTATUS)
checked using only one read of FTMxSTATUS register. And all CHnF bits can be cleared by a read of
FTMxSTATUS register followed by a write 0x00 to FTMxSTATUS register.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
CH6F
0
0
6
Table 11-8. FTMxSTATUS Field Descriptions
CH5F
5
0
0
CH4F
0
0
4
NOTE
Description
CH3F
0
0
3
CH2F
0
0
2
CH1F
Freescale Semiconductor
1
0
0
CH0F
0
0
0