mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 387

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16.5.2
In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL multiplication factor
of 512, the DCO output (MCGOUT) frequency is 16.78 MHz at high-range. If the DRS[1:0] bits are set
to %01, the multiplication factor is doubled to 1024, and the resulting DCO output frequency is 33.55 Mhz
at mid-range. If the DRS[1:0] bits are set to %10, the multiplication factor is set to 1536, and the resulting
DCO output frequency is 50.33 Mhz at high-range. Make sure that the resulting bus clock frequency does
not exceed the maximum specified bus clock frequency of the device.
Setting the DMX32 bit in MCGC4 to 1 increases the FLL multiplication factor to allow the 32.768 kHz
reference to achieve its maximum DCO output frequency. When the DRS[1:0] bits are set to %00, the
32.768 kHz reference can achieve a high-range maximum DCO output of 19.92 MHz with a multiplier of
608. When the DRS[1:0] bits are set to %01, the 32.768 kHz reference can achieve a mid-range maximum
DCO output of 39.85 MHz with a multiplier of 1216. When the DRS[1:0] bits are set to %10, the 32.768
kHz reference can achieve a high-range maximum DCO output of 59.77 MHz with a multiplier of 1824.
Make sure that the resulting bus clock frequency does not exceed the maximum specified bus clock
frequency of the device.
In FBI and FEI modes, setting the DMX32 bit is not recommended. If the internal reference is trimmed to
a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the
microcontroller system clock out of specification and damage the part.
16.5.3
When switching between operational modes of the MCG, certain configuration bits must be changed in
order to properly move from one mode to another. Each time any of these bits are changed (PLLS, IREFS,
CLKS, or EREFS), the corresponding bits in the MCGSC register (PLLST, IREFST, CLKST, or
OSCINIT) must be checked before moving on in the application software.
Additionally, care must be taken to ensure that the reference clock divider (RDIV) is set properly for the
mode being switched to. For instance, in PEE mode, if using a 4 MHz crystal, RDIV must be set to %001
(divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required
frequency between 1 and 2 MHz.
If switching to FBE or FEE mode, first setting the DIV32 bit will ensure a proper reference frequency is
sent to the FLL clock at all times.
In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL multiplication factor
between 512, 1024, and 1536 with the DRS[1:0] bits in MCGC4. Writes to the DRS[1:0] bits will be
ignored if LP=1 or PLLS=1.
The RDIV and IREFS bits should always be set properly before changing the PLLS bit so that the FLL or
PLL clock has an appropriate reference clock frequency to switch to. The table below shows MCGOUT
Freescale Semiconductor
Using a 32.768 kHz Reference
MCG Mode Switching
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Multipurpose Clock Generator (MCGV3)
16-19