mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 235

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

If the channel input does not have a filter enabled, then the input signal is always delayed 3 rising edges
of the system clock (two rising edges to the synchronizer plus one more rising edge to the edge detector).
In other words, the CHnF bit is set on the third rising edge of the system clock after a valid edge occurs on
the channel input pin .
11.4.4.1
The filter function is only available on channels 0, 1, 2 and 3.
Firstly the input signal is synchronized by the system clock (synchronizer block in
Following synchronization, the input signal enters the filter block
change in the input signal, the 5-bit counter is reset and starts counting up. As long as the new state is stable
on the input, the counter continues to increment. If the 5-bit counter overflows (the counter exceeds the
value of the CHnFVAL[3:0] bits), the state change of the input signal is validated. It is then transmitted as
a pulse edge to the edge detector.
If the opposite edge appears on the input signal before validation (counter overflow), the counter is reset.
At the next input transition, the counter will start counting again. Any pulse that is shorter than the
minimum value selected by CHnFVAL[3:0] bits (x 4 system clocks) is regarded as a glitch and is not
passed on to the edge detector. A timing diagram of the input filter is shown in
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case the input signal is delayed 3
rising edges of the system clock. If (CHnFVAL[3:0] not = 0000) then the input signal is delayed by the
Freescale Semiconductor
channel (n) input
system clock
* Filtering function is only available in the inputs of channel 0, 1, 2 and 3
Filter for input capture mode
Input capture mode is only available when (FTMEN = 0) and
(FTMxCNTINH:FTMxCNTINL = 0x0000). Input capture mode with
(FTMEN = 1) or (FTMxCNTINH:FTMxCNTINL not = 0x0000) is not
recommended and its results are not guaranteed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
D
CLK
synchronizer
Q
D
CLK
Q
Figure 11-32. Input capture mode
Filter*
NOTE
enabled?
is filter
0
1
detector
falling edge
edge
rising edge
0
0
edge selected?
edge selected?
(Figure
was falling
was rising
1
0
0
1
11-33). When there is a state
CHnIE
CHnF
Figure
FTMxCnVH:L[15:0]
Figure
FlexTimer Module (FTMV1)
FTM counter
11-34.
channel (n) interrupt
11-32).
11-35