mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 431

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

19.2
The SPI optionally shares four port pins. The function of these pins depends on the settings of SPI control
bits. When the SPI is disabled (SPI1C1[SPE] is cleared), these four pins revert to being general-purpose
port I/O pins that are not controlled by the SPI.
19.2.1
When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master,
this pin is the serial clock output.
19.2.2
When the SPI is enabled as a master and SPI pin control zero bit (SPI1C2[SPC0]) is cleared (not
bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and
SPI1C2[SPC0] is cleared, this pin is the serial data input. If SPC0 is set to select single-wire bidirectional
mode and master mode is selected, this pin becomes the bidirectional data I/O pin (MOMI). Also, the
bidirectional mode output enable bit determines whether the pin acts as an input (SPI1C2[BIDIROE] = 0)
or an output (BIDIROE = 1). If SPC0 is set and slave mode is selected, this pin is not used by the SPI and
reverts to a general-purpose port I/O pin.
19.2.3
When the SPI is enabled as a master and SPI pin control zero (SPI1C2[SPC0]) is cleared (not bidirectional
mode), this pin is the serial data input. When the SPI is enabled as a slave and SPC0 is cleared, this pin is
the serial data output. If SPC0 is set to select single-wire bidirectional mode and slave mode is selected,
this pin becomes the bidirectional data I/O pin (SISO) and the bidirectional mode output enable bit
determines whether the pin acts as an input (BIDIROE = 0) or an output (BIDIROE = 1). If SPC0 is set
and master mode is selected, this pin is not used by the SPI and reverts to being a general-purpose port I/O
pin.
19.2.4
When the SPI is enabled as a slave, this pin is the low-true slave select input. When the SPI is enabled as
a master and mode fault enable is off (SPI1C2[MODFEN] = 0), this pin is not used by the SPI and reverts
to a general-purpose port I/O pin. When the SPI is enabled as a master and MODFEN is set, the slave select
Freescale Semiconductor
External Signal Description
SPSCK — SPI Serial Clock
MOSI — Master Data Out, Slave Data In
MISO — Master Data In, Slave Data Out
SS — Slave Select
Bus Clock
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
1, 2, 3, 4, 5, 6, 7, or 8
Figure 19-3. SPI Baud Rate Generation
SPI1BR[SPPR]
Prescaler
Divide By
2, 4, 8, 16, 32, 64, 128, or 256
Clock Rate Divider
SPI1BR[SPR]
Divide By
8-Bit Serial Peripheral Interface (SPIV3)
Master
SPI
Bit Rate
19-5