mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 504

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22.3.2
The 32-bit XCSR is partitioned into two sections: the upper byte contains status and command bits always
accessible to the BDM interface, even if debug mode is disabled. This status byte is also known as
XCSR_SB. The lower 24 bits contain fields related to the generation of automatic SYNC_PC commands,
which can be used to periodically capture and display the current program counter (PC) in the PST trace
buffer (if properly configured).
There are multiple ways to reference the XCSR. They are summarized in
22-12
Reset
Reset
DRc: 0x01 (XCSR)
Field
DDH
FID
1
0
W
W
WRITE_XCSR_BYTE Writes XCSR[31
WDEBUG instruction Writes XCSR[23
R CPU
R
READ_XCSR_BYTE Reads XCSR[31
HALT
WRITE_DREG
READ_DREG
31
15
0
0
0
Method
Force ipg_debug. The core generates this output to the device, signaling it is in debug mode.
0 Do not force the assertion of ipg_debug
1 Force the assertion of ipg_debug
Disable ipg_debug due to a halt condition. The core generates an output to the other modules in the device,
signaling it is in debug mode. By default, this output signal is asserted when the core halts.
0 Assert ipg_debug if the core is halted
1 Negate ipg_debug due to the core being halted
Extended Configuration/Status Register (XCSR)
STOP
CPU
30
14
0
0
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
29
13
0
0
0
Figure 22-5. Extended Configuration/Status Register (XCSR)
Reads XCSR[31
Writes XCSR[23
is a privileged supervisor-mode instruction.
ESEQC
CSTAT
28
12
0
0
0
Table 22-5. CSR Field Descriptions (continued)
Table 22-6. XCSR Reference Summary
27
11
0
0
0
–
–
–
–
–
CLK
SW
24] from the BDM interface. Available in all modes.
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] from the BDM interface. Classified as a non-intrusive BDM command.
0] during the core’s execution of WDEBUG instruction. This instruction
26
10
24] from the BDM interface. Available in all modes.
0
0
0
ERASE
SEC
25
0
9
0
0
BDM
Description
EN
24
0
8
0
0
Reference Details
23
0
0
7
0
0
22
0
0
0
0
6
21
0
0
0
0
5
Table
20
0
0
0
0
4
22-6.
Access: Supervisor write-only
19
Freescale Semiconductor
0
0
0
0
3
18
0
0
0
2
APCSC
BDM read/write
17
0
0
0
1
APC
ENB
16
0
0
0
0