mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 446

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16-Bit Serial Peripheral Interface (SPI16)
20-6
Reset
SPTIE
MSTR
CPHA
CPOL
Field
SPIE
SPE
7
6
5
4
3
2
W
R
SPIE
FIFOMODE=0
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
FIFOMODE=1
SPI Read FIFO Full Interrupt Enable — This bit when set enables the SPI to interrupt the CPU when the
Receive FIFO is full. An interrupt will occur when SPRF flag is set or MODF is set.
0 Read FIFO Full Interrupts are disabled
1 Read FIFO Full Interrupts are enabled
SPI System Enable — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
If SPE is cleared, SPI is disabled and forced into idle state, and all status bits in the SPIxS register are reset.
0 SPI system inactive
1 SPI system enabled
SPI Transmit Interrupt Enable —
FIFOMODE=0
This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit
buffer is empty (SPTEF is set)
FIFOMODE=1
This is the interrupt enable bit for SPI transmit FIFO empty (SPTEF). An interrupt occurs when the SPI transmit
FIFO is empty (SPTEF is set)
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
Master/Slave Mode Select — This bit selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules,
the SPI modules must have identical CPOL values.
This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device.
Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to
0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 First edge on SPSCK occurs at the start of the first cycle of a data transfer
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Section 20.4.6, “SPI Clock
SPE
0
6
Section 20.4.6, “SPI Clock
Figure 20-3. SPI Control Register 1 (SPIxC1)
Table 20-1. SPIxC1 Field Descriptions
SPTIE
0
5
Formats”
MSTR
Formats”
for more details.
0
4
Description
for more details.
CPOL
3
0
CPHA
1
2
Freescale Semiconductor
SSOE
0
1
LSBFE
0
0