mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 497

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

While in halt mode, the core waits for serial background commands rather than executing instructions from
the application program.
Figure 22-2
controls the BDC clock source. When CLKSW is set, the BDC serial clock frequency is half the CPU
clock. When CLKSW is cleared, the BDC serial clock is supplied from an alternate clock source.
The ENBDM bit determines if the device can be placed in halt mode, if the core and BDC serial clocks
continue to run in STOP modes, and if the regulator can be placed into standby mode. Again, if booting to
halt mode, XCSR[ENBDM, CLKSW] are automatically set.
If ENBDM is cleared, the ColdFire core treats the HALT instruction as an illegal instruction and generates
a reset (if CPUCR[IRD] is cleared) or an exception (if CPUCR[IRD] is set) if execution is attempted.
If XCSR[ENBDM] is set, the device can be restarted from STOP/WAIT via the BDM interface.
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Illegal address reset and CSR2[IADHR]=1 or
A BACKGROUND command is received through the BKGD pin. If necessary, this wakes the
device from STOP/WAIT modes.
A properly-enabled (XCSR[ENBDM] is set) HALT instruction is executed
Encountering a BDM breakpoint and the trigger response is programmed to generate a halt
Reaching a PSTB trace buffer full condition when operating in an obtrusive recording mode
(CSR2[PSTBRM] is set to 01 or 11)
Illegal op reset and CSR2[IOPHR]=1 or
COP reset and CSR2[COPHR]=1 or
(POR or BDFR=1) with BKGD=0 or
contains a simplified view of the V1 ColdFire debug mode states. The XCSR[CLKSW] bit
BDFR, BFHBR, and BKGD=1 or
BDFR=1 and BFHBR=0 or
BDFR and BFHBR= 1 or
POR with BKGD=1 or
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
any other reset
CPU clock/2 is used
Figure 22-2. Debug Modes State Transition Diagram
as the BDM clock
BDM & CPU clocks are not
enabled in STOP modes
State
Any
Debug not enabled
CLKSW=1
CLKSW=0
ENBDM=1
ENBDM=0
Operation
Normal
Debug
Halt
clear ENBDM
command
BDM GO
via BDM
BACKGROUND command,
ENBDM
ENBDM=1
Operation
Normal
HALT instruction, or
Set
Version 1 ColdFire Debug (CF1_DEBUG)
Return to Halt via
BDM breakpoint trigger
CPU clocks continue
during STOP modes
Debug is enabled
22-5