mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 501
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mcf51ac256a
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Mcf51ac Flexis
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DRc[4:0]: 0x00 (CSR)
The ColdFire debug architecture supports a number of hardware breakpoint registers that can be
configured into single- or double-level triggers based on the PC or operand address ranges with an optional
inclusion of specific data values. The triggers can be configured to halt the processor or generate a debug
interrupt exception. Additionally, these same breakpoint registers can be used to specify start/stop
conditions for recording in the PST trace buffer.
The core includes four PC breakpoint triggers and a set of operand address breakpoint triggers with two
independent address registers (to allow specification of a range) and an optional data breakpoint with
masking capabilities. Core breakpoint triggers are accessible through the serial BDM interface or written
through the supervisor programming model using the WDEBUG instruction.
22.3.1
CSR defines the debug configuration for the processor and memory subsystem and contains status
information from the breakpoint logic. CSR is accessible from the programming model using the
WDEBUG instruction and through the BDM port using the READ_DREG and WRITE_DREG
commands.
Freescale Semiconductor
Reset
Reset
W
W
R
R
31
15
0
0
0
Configuration/Status Register (CSR)
Debug control registers can be written by the external development system
or the CPU through the WDEBUG instruction. These control registers are
write-only from the programming model and they can be written through the
BDM port using the WRITE_DREG command. In addition, the four
configuration/status registers (CSR, XCSR, CSR2, CSR3) can be read
through the BDM port using the READ_DREG command.
TRC
30
14
0
0
BSTAT
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
29
13
0
0
0
28
12
0
0
Figure 22-4. Configuration/Status Register (CSR)
DDC
FOF
27
11
0
0
TRG HALT BKPT
UHE
26
10
0
0
25
0
0
9
BTB
NOTE
24
0
0
8
23
1
0
0
7
NPL
22
0
0
6
HRL
IPI
21
0
0
5
Version 1 ColdFire Debug (CF1_DEBUG)
SSM
20
1
4
0
Access: Supervisor write-only
19
0
0
0
0
3
BKD
18
0
0
0
2
BDM read/write
VBD
FID
17
1
0
1
DDH
IPW
22-9
16
0
0
0
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