mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 146
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ColdFire Core
7.3.3.3
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if an
illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is
generated as detailed below. There is one special case involving the ILLEGAL opcode (0x4AFC)
attempted execution of this instruction always generates an illegal instruction exception, regardless of the
state of the CPUCR[IRD] bit.
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See
definition is shown in
7-16
Opword[Line]
15
0xC
0xD
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xE
0xF
14
Illegal Instruction Exception
Line
Move Byte
Move Word
Logical OR (OR)
Write DDATA (WDDATA), Write Debug (WDEBUG)
Bit manipulation, Arithmetic and Logical Immediate
Move Long
Miscellaneous
Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
Subtract (SUB), Subtract Extended (SUBX)
Move 3-bit Quick (MOV3Q)
Compare (CMP), Exclusive-OR (EOR)
Logical AND (AND), Multiply Word (MUL)
Add (ADD), Add Extended (ADDX)
Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
13
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 7-11. ColdFire Instruction Operation Word (Opword) Format
Table
12
7-10.
11
Table 7-10. ColdFire Opword Line Definition
10
OpMode
9
8
Instruction Class
7
6
5
Figure
Mode
4
7-11. The opword line
Effective Address
3
Freescale Semiconductor
2
Register
1
;
0
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