mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 252

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
If (CLKS[1:0] = 00) then FTMxCnVH:L registers are updated when their second byte is written
(independent of FTMEN bit). If (CLKS[1:0] not = 00) then FTMxCnVH:L registers are updated with their
write buffer according to the FTMEN bit. If (CLKS[1:0] not = 00 and FTMEN = 1) then FTMxCnVH:L
registers are updated by PWM synchronization
not = 00 and FTMEN = 0) then FTMxCnVH:L registers are updated according to the selected mode, that
is:
11.4.11 PWM synchronization
PWM synchronization provides an opportunity to update registers with the contents of their write buffers.
It can also be used to synchronize two or more FlexTimer modules on the same MCU.
PWM synchronization updates the FTMxMODH:L and FTMxCnVH:L registers with their write buffers.
It is also possible to force the FTM counter to its initial value and update the CHnOM bits in
FTMxOUTMASK using PWM synchronization.
11.4.11.1 Hardware Trigger
Each hardware trigger (input signals: trigger_0, trigger_1 and trigger_2) is synchronized by the system
clock.
A rising edge on the selected hardware trigger input (trigger n event) initiates PWM synchronization. A
hardware trigger is selected when its enable bit is set (TRIGn = 1 where n = 0, 1 or 2). The TRIGn bit is
cleared when 0 is written to it or when the PWM synchronization (initiated by a selected hardware trigger
event) is completed.
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If (selected mode is not CPWM mode) then FTMxMODH:L registers are updated after both bytes
have been written and the FTM counter changes from (FTMxMODH:L) to (FTMxCNTINH:L). If
the FTM counter is a free-running counter then this update is made when the FTM counter changes
from 0xFFFF to 0x0000.
If (selected mode is CPWM mode) then FTMxMODH:L registers are updated after both bytes have
been written and the FTM counter changes from (FTMxMODH:L) to (FTMxMODH:L - 0x0001).
If (selected mode is output compare mode), then FTMxCnVH:L registers are updated after their
second byte is written and on the next change of the FTM counter (end of the prescaler counting).
If (selected mode is EPWM mode), then FTMxCnVH:L registers are updated after both bytes have
been written and the FTM counter changes from (FTMxMODH:L) to (FTMxCNTINH:L). If the
FTM counter is a free-running counter then this update is made when the FTM counter changes
from 0xFFFF to 0x0000.
If (selected mode is CPWM mode), then FTMxCnVH:L registers are updated after both bytes have
been written and the FTM counter changes from (FTMxMODH:L) to (FTMxMODH:L - 0x0001).
PWM synchronization is only available when (COMBINE = 1) and
(CPWMS = 0). PWM synchronizaton with (COMBINE = 0) or (CPWMS =
1) is not recommended and its results are not guaranteed.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(Section 11.4.11, “PWM
NOTE
synchronization). If (CLKS[1:0]
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