mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 532

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22.4.1.5.1
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct speed to use for serial communications until after it has analyzed the response to the SYNC
command.
To issue a SYNC command, the host:
Upon detecting the sync request from the host (which is a much longer low time than would ever occur
during normal BDC communications), the target:
22-40
1
2
3
SYNC_PC
WRITE_CREG
WRITE_DREG
WRITE_MEM.sz
WRITE_MEM.sz_WS
WRITE_Rn
WRITE_XCSR_BYTE
WRITE_CSR2_BYTE
WRITE_CSR3_BYTE
This column identifies if the command generates an ACK pulse if operating with acknowledge mode enabled. See
Section 22.4.1.5.3, “ACK_ENABLE,”
The SYNC command is a special operation which does not have a command code.
If a GO command is received while the processor is not halted, it performs no operation.
1. Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (bus clock or
2. Drives BKGD high for a brief speed-up pulse to get a fast rise time. (This speedup pulse is typically
3. Removes all drive to the BKGD pin so it reverts to high impedance.
4. Listens to the BKGD pin for the sync response pulse.
1. Waits for BKGD to return to a logic high.
Command
Mnemonic
device-specific alternate clock source).
one cycle of the host clock which is as fast as the maximum target BDC clock.)
SYNC
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Classification
Non-Intrusive
Non-Intrusive
Non-Intrusive
Non-Intrusive
Background
Background
Command
Available
Available
Available
Always
Always
Always
Active
Active
Table 22-25. BDM Command Summary (continued)
for addition information.
if Enb?
ACK
Yes
Yes
Yes
Yes
Yes
No
No
No
No
1
(0x11+4 x sz)/ad24/wd.sz/d/ss Write the appropriately-sized (sz) memory
(0x10+4 x sz)/ad24/wd.sz/d
(0xC0+CRN)/wd32/d
(0x80+CRN)/wd32/d
(0x40+CRN)/wd32/d
Command
Structure
0x0D/wd8
0x0E/wd8
0x0F/wd8
0x01/d
Display the CPU’s current PC and capture
it in the PST trace buffer
Write one of the CPU’s control registers
Write one of the debug module’s control
registers
Write the appropriately-sized (sz) memory
value to the location specified by the 24-bit
address
value to the location specified by the 24-bit
address and report status
Write the requested general-purpose
register (An, Dn) of the CPU
Write the most significant byte of the debug
module’s XCSR
Write the most significant byte of the debug
module’s CSR2
Write the most significant byte of the debug
module’s CSR3
Description
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