mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 519

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.3.10 Data Breakpoint and Mask Registers (DBR, DBMR)
DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting
corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the WRITE_DREG commands.
The DBR supports aligned and misaligned references.
processor address, access size, and location within the 32-bit data bus.
Freescale Semiconductor
Address
Address
Field
Field
Field
Field
Mask
31–0
31–0
31–0
31–0
Data
DRc[4:0]: 0x0E (DBR)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for
specific addresses are programmed into ABLR.
High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.
Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
0 The corresponding DBR bit is compared to the appropriate bit of the processor’s local data bus
1 The corresponding DBR bit is ignored
W
R
0x0F (DBMR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-15. Data Breakpoint & Mask Registers (DBR, DBMR)
Table 22-21. DBMR Field Descriptions
Table 22-19. ABHR Field Description
Table 22-18. ABLR Field Description
Table 22-20. DBR Field Descriptions
Data (DBR); Mask (DBMR)
Description
Description
Description
Description
Table 22-22
shows the relationships between
Version 1 ColdFire Debug (CF1_DEBUG)
Access: Supervisor write-only
8
7
6
5
BDM write-only
4
3
2
1
0
22-27