mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 137

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

7.2.7
The CPUCR provides supervisor mode configurability of specific core functionality. Certain hardware
features can be enabled/disabled individually based on the state of the CPUCR.
Freescale Semiconductor
Field
ARD
Reset
BDM: 0x802 (CPUCR)
IRD
IME
IAE
31
30
29
28
W
R
Load: 0xE2 (CPUCR)
Store: 0xC2 (CPUCR)
ARD IRD IAE IME BWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 – – – – – – – – – – – – – – – – – – – –
BDM: 0x801 (VBR)
Address-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by an address error, a bus error, an RTE format error, or a fault-on-fault halt condition.
0 The detection of these types of exception conditions or the fault-on-fault halt condition generate a reset event.
1 No reset is generated in response to these exception conditions.
Instruction-related reset disable. Used to disable the generation of a reset event in response to a processor exception
caused by the attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line A, illegal
line F instructions, or a privilege violation.
0 The detection of these types of exception conditions generate a reset event.
1 No reset is generated in response to these exception conditions.
Interrupt acknowledge (IACK) enable. Forces the processor to generate an IACK read cycle from the interrupt
controller during exception processing to retrieve the vector number of the interrupt request being acknowledged. The
processor’s execution time for an interrupt exception is slightly improved when this bit is cleared.
0 The processor uses the vector number provided by the interrupt controller at the time the request is signaled.
1 IACK read cycle from the interrupt controller is generated.
Interrupt mask enable. Forces the processor to raise the interrupt level mask (SR[I]) to 7 during every interrupt
exception.
0 As part of an interrupt exception, the processor sets SR[I] to the level of the interrupt being serviced.
1 As part of an interrupt exception, the processor sets SR[I] to 7. This disables all level 1-6 interrupt requests but
31
0
W
allows recognition of the edge-sensitive level 7 requests.
R 0 0 0 0 0 0 0 0
CPU Configuration Register (CPUCR)
30
Load: 0xE1 (VBR)
Store: 0xC1 (VBR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
29
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
28
0
27
0
Figure 7-8. CPU Configuration Register (CPUCR)
26
0
0
Figure 7-7. Vector Base Register (VBR)
FSD
25
Table 7-3. CPUCR Field Descriptions
0
Address
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Base
0
0
– – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – – – – – – – – – – – – –
Description
Access: Supervisor read/write
8
7
Access: Supervisor read/write
6
8
5
7
BDM read/write
4
6
3
5
BDM read/write
2
4
ColdFire Core
1
3
0
2
1
7-7
0