mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 546

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
Figure 22-22
command is used as an example:
This process is referred to as cycle stealing. The READ_MEM.B appears as a single-cycle operation to the
processor, even though the pipelined nature of the Operand Execution Pipeline requires multiple CPU
clock cycles for it to actually complete. After that, the debug module tracks the execution of the
READ_MEM.b command as the processor resumes the normal flow of the application program. After
detecting the READ_MEM.B command is done, the BDC issues an ACK pulse to the host controller,
indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates
the data-read portion of the command.
Unlike a normal bit transfer, where the host initiates the transmission by issuing a negative edge in the
BKGD pin, the serial interface ACK handshake pulse is initiated by the target MCU. The hardware
handshake protocol in
should follow these timing relationships to avoid the risks of an electrical conflict at the BKGD pin.
The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not
acknowledged by an ACK pulse, the host first needs to abort the pending command before issuing a new
BDC command. When the CPU enters a stop mode at about the same time the host issues a command that
requires CPU execution, the target discards the incoming command. Therefore, the command is not
acknowledged by the target, meaning that the ACK pulse is not issued in this case. After a certain time,
the host could decide to abort the ACK protocol to allow a new command. Therefore, the protocol provides
a mechanism where a command (a pending ACK) could be aborted. Unlike a regular BDC command, the
ACK pulse does not provide a timeout. In the case of a STOP instruction where the ACK is prevented from
being issued, it would remain pending indefinitely if not aborted. See the handshake abort procedure
described in
22-54
BKGD PIN
1. The 8-bit command code is sent by the host, followed by the address of the memory location to be
2. The target BDC decodes the command and sends it to the CPU.
3. Upon receiving the BDC command request, the CPU schedules a execution slot for the command.
4. The CPU temporarily stalls the instruction stream at the scheduled point, executes the
read.
READ_MEM.B command and then continues.
Section 22.4.1.7, “Hardware Handshake Abort Procedure.”
shows the ACK handshake protocol in a command level timing diagram. A READ_MEM.B
READ_MEM.B
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 22-22
HOST
Figure 22-22. Handshake Protocol at Command Level
ADDRESS[23–0]
TARGET
DEBUG DECODES
THE COMMAND
specifies the timing when the BKGD pin is being driven, so the host
CPU EXECUTES THE
COMMAND
READ_MEM.B
TARGET
RETRIEVED
BDC ISSUES THE
ACK PULSE (NOT TO SCALE)
BYTE IS
HOST
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NEW BDC COMMAND
HOST
TARGET