mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 66

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Memory
For example, if the bus clock frequency is 25 MHz, FCDIV[FDIV] must be set to 0x0F (001111) and the
FCDIV[PRDIV8] bit set to 1. The resulting FCLK frequency is then 195 kHz. In this case, the flash
program and erase algorithm timings are increased over the optimum target by:
If the FCDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCDIV
register has not been written since the last reset. If the FCDIV register has not been written to, the flash
command loaded during a command write sequence will not execute and FSTAT[FACCERR] will be set.
4-22
Program and erase command execution time will increase proportionally
with the period of FCLK. Programming or erasing the flash memory with
FCLK < 150 kHz must be avoided. Setting FCDIV to a value such that
FCLK < 150 kHz can destroy the flash memory due to overstress. Setting
FCDIV to a value such that FCLK > 200 kHz can result in incomplete
programming or erasing of the flash memory cells.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(200 – 195) ÷ 200 = 3%
CAUTION
Freescale Semiconductor
Eqn. 4-1