mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 285

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

the transition from master to slave mode does not generate a stop condition. Meanwhile, a status bit is set
by hardware to indicate loss of arbitration.
12.4.1.7
Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line affects all
the devices connected on the bus. The devices start counting their low period and after a device’s clock has
gone low, it holds the SCL line low until the clock high state is reached. However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock remains within
its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period.
Devices with shorter low periods enter a high wait state during this time (see
devices concerned have counted off their low period, the synchronized clock SCL line is released and
pulled high. There is then no difference between the device clocks and the state of the SCL line and all the
devices start counting their high periods. The first device to complete its high period pulls the SCL line
low again.
12.4.1.8
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such a case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
12.4.1.9
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
Freescale Semiconductor
SCL1
SCL2
SCL
Clock Synchronization
Handshaking
Clock Stretching
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Internal Counter Reset
Figure 12-9. IIC Clock Synchronization
Delay
Start Counting High Period
Figure
Inter-Integrated Circuit (IICV2)
12-9). When all
12-13