mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 85

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the microcontroller exits stop mode.
When the 1 kHz LPO clock source is selected, the COP counter is re-initialized to zero upon entry to stop
mode. The COP counter begins from zero after the microcontroller exits stop mode.
5.3.2
By default, the V1 ColdFire core generates a MCU reset when attempting to execute an illegal instruction
(except for the ILLEGAL opcode), illegal line-A instruction, illegal line-F instruction, or a supervisor
instruction while in user mode (privilege violation). The user may set CPUCR[IRD] to generate the
appropriate exception instead of forcing a reset.
5.3.3
By default, the V1 ColdFire core generates a MCU reset when detecting an address error, bus error
termination, RTE format error, or fault-on-fault condition. The user may set CPUCR[ARD] to generate the
appropriate exception instead of forcing a reset, or simply halt the processor in response to the
fault-on-fault condition.
5.4
The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the
interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest
priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt
requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask
value (I) contained in bits 10:8 of the processor’s status register (SR). If the priority level is greater than
the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates
interrupt exception processing.
Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6
are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct
operation, the ColdFire processor requires that, once asserted, the interrupt source remain asserted until
explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU does the following tasks in order:
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1. enters supervisor mode,
2. disables trace mode,
3. uses the vector provided by the INTC when the interrupt was signaled (if CPUCR[IACK] = 0) or
explicitly fetches an 8-bit vector from the INTC (if CPUCR[IACK] = 1).
Interrupts & Exceptions
Illegal Opcode Detect (ILOP)
Illegal Address Detect (ILAD)
The attempted execution of the STOP instruction with SOPT[STOPE,
WAITE] cleared is treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM]
cleared is treated as an illegal instruction.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
NOTE
Resets, Interrupts, and General System Control
5-3