mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 452

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16-Bit Serial Peripheral Interface (SPI16)
For FIFO management there are two other important flags that are used to help make the operation more
efficient when transfering large amounts of data. These are the Receive FIFO Nearly Full Flag
(RNFULLF) and the Transmit FIFO Nearly Empty Flag (TNEAREF). Both these flags provide a
“watermark” feature of the FIFOs to allow continuous transmissions of data when running at high speed.
The RNFULLF flag can generate an interrupt if the RNFULLIEN bit in the SPIxC3 Register is set which
allows the CPU to start emptying the Receive FIFO without delaying the reception of subsequent bytes.
The user can also determine if all data in Receive FIFO has been read by monitoring the RFIFOEF flag.
The TNEAREF flag can generate an interrupt if the TNEARIEN bit n the SPIxC3 Register is set which
allows the CPU to start filling the Transmit FIFO before it is empty and thus provide a mechanism to have
no breaks in SPI transmission.
Figure 20-7
20.3.5
20-12
Reset
Reset
Reset
W
W
W
R
R
R
SPRF
SPRF
Bit 15
SPI Data Registers (SPIxDH:SPIxDL)
and
0
0
0
7
7
7
SPIxS and both TX and RX fifos gets reset due to change in SPIMODE,
FIFOMODE or SPE. PoR values of SPIxS are show in
Figure 20-8
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 20-7. Reset values of SPIxS after PoR with FIFOMODE = 0
Figure 20-8. Reset values of SPIxS after PoR with FIFOMODE = 1
SPMF
SPMF
14
0
0
0
6
6
6
shows the reset values due to change of modes after PoR.
Figure 20-9. SPI Data Register High (SPIxDH)
SPTEF
SPTEF
13
1
1
0
5
5
5
MODF
MODF
NOTE
12
0
0
0
4
4
4
RNFULLF
RNFULLF
11
3
0
3
0
3
0
Figure
TNEAREF
TNEAREF
10
0
1
0
2
2
2
20-7.
TXFULLF
TXFULLF
Freescale Semiconductor
0
0
9
0
1
1
1
RFIFOEF
RFIFOEF
Bit 8
0
1
0
0
0
0