mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 433

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

19.4.2
This read/write register controls optional features of the SPI system. Bits 7, 6, 5, and 2 are reserved and
always read 0.
Freescale Semiconductor
LSBFE
SPTIE
MSTR
CPHA
SSOE
CPOL
Field
5
4
3
2
1
0
SPI Control Register 2 (SPI1C2)
SPI Transmit Interrupt Enable. This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity. This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase. This bit selects one of two clock formats for different synchronous serial peripheral devices. Refer
to
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Slave Select Output Enable. This bit is used with the mode fault enable (SPI1C2[MODFEN]) bit and the
master/slave (MSTR) control bit to determine the function of the SS pin as shown in
lsb First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
MODFEN
Section 19.5.1, “SPI Clock
Ensure that the SPI should not be disabled (SPE = 0) at the same time as a
bit change to SPI1C1[CPHA]. These changes should be performed as
separate operations or unexpected behavior may occur.
0
0
1
1
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
SSOE
Table 19-1. SPI1C1 Field Descriptions (continued)
0
1
0
1
Section 19.5.1, “SPI Clock
Formats”
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
Table 19-2. SS Pin Function
SS input for mode fault
Automatic SS output
Master Mode
for more details.
NOTE
Description
Formats”
for more details.
Slave select input
Slave select input
Slave select input
Slave select input
Slave Mode
8-Bit Serial Peripheral Interface (SPIV3)
Table
19-2.
19-7