mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 423

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

the end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0
so all receivers wake up in time to look at the first character(s) of the next message.
18.3.3.2.1
When wake is cleared, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared
automatically when the receiver detects a full character time of the idle-line level. The M control bit selects
8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character
time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE
flag. The receiver wakes up and waits for the first data character of the next message that sets the RDRF
flag and generates an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE flag and
generates an interrupt if enabled, regardless of whether RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT is cleared, the
idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward
the full character time of idle. When ILT is set, the idle bit counter does not start until after a stop bit time,
so the idle detection is not affected by the data in the last character of the previous message.
18.3.3.2.2
When wake is set, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared
automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth
bit when M is cleared and ninth bit when M is set).
Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use
in address frames. The logic 1 msb of an address frame clears the RWU bit before the stop bit is received
and sets the RDRF flag. In this case, the character with the msb set is received even though the receiver
was sleeping during most of this character time.
18.3.4
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the
cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.
Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF, and LBKDIF events.
A third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can be
separately masked by local interrupt enable masks. The flags can be polled by software when the local
masks are cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that can optionally generate hardware interrupt requests. Transmit
data register empty (TDRE) indicates when there is room in the transmit data buffer to write another
transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt is
requested when TDRE is set. Transmit complete (TC) indicates that the transmitter is finished transmitting
all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is often used
in systems with modems to determine when it is safe to turn off the modem. If the transmit complete
interrupt enable (TCIE) bit is set, a hardware interrupt is requested when TC is set. Instead of hardware
Freescale Semiconductor
Interrupts and Status Flags
Idle-Line Wakeup
Address-Mark Wakeup
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Serial Communication Interface (SCI)Serial Communications Interface (SCIV4)
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