mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 80

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Memory
The MCU cannot be unsecured by using the backdoor key access sequence in background debug mode
(BDM).
4.4.8
4.4.8.1
On each reset, the flash module executes a reset sequence to hold CPU activity while reading the following
resources from the flash block:
4.4.8.2
If a reset occurs while any flash command is in progress, that command will be immediately aborted. The
state of the flash array address being programmed or the sector/block being erased is not guaranteed.
4.4.8.3
Before any program or erase command can be accepted, the flash clock divider (CSR3[FCDIV]) must be
written to set the internal clock for the flash module to a frequency (f
One period of the resulting clock (1/f
pulses. An integer number of these timing pulses are used by the command processor to complete a
program or erase command.
Program and erase times are given in the MCF51AC256 Series Data Sheet, order number MCF51AC256.
4.5
This device includes circuitry to prevent unauthorized access to the contents of flash and RAM memory.
When security is engaged, BDM access is restricted to the upper byte of the ColdFire CSR, XCSR, and
CSR2 registers. RAM, flash memory, peripheral registers and most of the CPU register set are not
available via BDM. Programs executing from internal memory have normal access to all MCU memory
locations and resources.
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC[1:0]) in the
FOPT register. During reset, the contents of the nonvolatile location, NVOPT, are copied from flash into
the working FOPT register in high-page register space. A user engages security by programming the
NVOPT location which can be done at the same time the flash memory is programmed. The 1:0 state
engages security and the other three combinations disengage security. Note that security is implemented
differently than on the pin-compatible MC9S08AC128 family of devices. This is a result of differences
inherent in the S08 and ColdFire MCU architectures.
4-36
MCU control parameters (see
Flash protection byte (see
Flash nonvolatile byte (see
Flash security byte (see
Security
Resets
Flash Reset Sequence
Reset While Flash Command Active
Program and Erase Times
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Section 4.2.2
Section 4.2.2
Section
FCLK
Section
) is used by the command processor to time program and erase
4.2.2)
and
4.2.2)
and
Section
Section
4.4.2.2)
4.4.2.4)
FCLK
) between 150 kHz and 200 kHz.
Freescale Semiconductor

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