mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 556

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22.4.4.2
As PST and DDATA values are captured and loaded in the trace buffer, each entry is six bits in size
therefore, the type of the entry can easily be determined when post-processing the PSTB. See
Figure
22.4.4.3
In this section, an example showing the behavior of the PST/DDATA functionality is detailed. Consider
the following interrupt service routine that counts the interrupt, negates the IRQ, performs a software
IACK, and then exits. This example is presented here because it exercises a considerable set of the
PST/DDATA capabilities.
01074: 46fc 2700
01078: 2f08
0107a: 2f00
0107c: 302f 0008
01080: e488
01082: 0280 0000 00ff
01088: 207c 0080 1400
0108e: 52b0 0c00
01092: 11c0 a021
01096: 1038 a020
0109a: 4e71
0109c: 71b8 ffe0
010a0: 0c80 0000 0041
010a6: 6f08
010a8: 52b9 0080 145c
010ae: 60de
010b0: 201f
010b2: 205f
010b4: 4e73
This ISR executes mostly as straight-line code: there is a single conditional branch @ PC = 0x10A6, which
is taken in this example. The following description includes the PST and DDATA values generated as this
22-64
22-27.
1
PSTB[DDATA]
PSTB[DDATA]
Depending on which nibble is displayed (as determined by CSR[9:8]), Address[3:0] sequentially
(least-to-most-significant nibble order) displays four bits of the real CPU address [16:1] or [24:1].
PST Trace Buffer (PSTB) Entry Format
PST/DDATA Example
PSTB[PST]
Address
Reset:
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Data
_isr_entry1:
_isr_exit:
_isr:
Figure 22-27. V1 PST/DDATA Trace Buffer Entry Format
mov.w
mov.l
mov.l
mov.w
lsr.l
andi.l
mov.l
addq.l
mov.b
mov.b
nop
mvz.b
cmpi.l
ble.b
addq.l
bra.b
mov.l
mov.l
rte
—
0
1
1
5
&0x2700,%sr
%a0,-(%sp)
%d0,-(%sp)
(8,%sp),%d0
&2,%d0
&0xff,%d0
&int_count,%a0
&1,(0,%a0,%d0.l*4) # count the interrupt
%d0,IGCR0+1.w
IGCR0.w,%d0
SWIACK.w,%d0
%d0,&0x41
_isr_exit
&1,swiack_count
_isr_entry1
(%sp)+,%d0
(%sp)+,%a0
R/W
—
0
4
—
3
# disable interrupts
# save a0
# save d0
# load format/vector word
# align vector number
# isolate vector number
# base of interrupt counters
# negate the irq
# force the write to complete
# synchronize the pipelines
# software iack: pending irq?
# level 7 or none pending?
# yes, then exit
# increment the swiack count
# continue at entry1
# restore d0
# restore a0
# exit
PST[4:0]
—
2
Address[3:0]
Data[3:0]
1
—
1
Freescale Semiconductor
—
0