mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 221

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

The FTMxCOMBINE0 register configures the control bits for channels 0 and 1; FTMxCOMBINE1 for
channels 2 and 3; FTMxCOMBINE2 for channels 4 and 5; and FTMxCOMBINE3 for channels 6 and 7.
11.3.15 FTM Deadtime Insertion Control Register (FTMxDEADTIME)
This read/write register selects the deadtime prescaler factor and deadtime value. All FTM channels use
this clock prescaler and this deadtime value for the deadtime insertion.
Freescale Semiconductor
Reset
W
R
COMBINE
FAULTEN
SYNCEN
COMP
DTEN
Field
6
5
4
1
0
0
0
7
Figure 11-17. FTM Function For Linked Channels Register (FTMxCOMBINEm)
The channel (n) is the even channel and the channel (n+1) is the odd channel
of a pair of channels.
Fault control enable. The FAULTEN bit enables the fault control in channels (n) and (n+1).
FAULTEN is write protected, this bit can only be written if WPDIS = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
Synchronization enable. The SYNCEN bit enables PWM synchronization of registers
FTMxC(n)VH:FTMxC(n)VL and FTMxC(n+1)VH:FTMxC(n+1)VL.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
Deadtime enable. The DTEN bit enables the deadtime insertion in the channels (n) and (n+1).
DTEN is write protected, this bit can only be written if WPDIS = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
Complement of channel (n). The COMP bit enables complementary mode for the combined channels.
In the complementary mode channel (n+1) output is the inverse of channel (n) output.
COMP is write protected, this bit can only be written if WPDIS = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
Combine channels (n) and (n+1). The COMBINE bit enables the combine feature for channels (n) and
(n+1).
COMBINE is write protected, this bit can only be written if WPDIS = 1.
0 Channels (n) and (n+1) are independent.
1 Combine mode is enabled for channels (n) and (n+1).
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
FAULTEN
0
6
Table 11-14. FTMxCOMBINEm Field Descriptions
SYNCEN
5
0
DTEN
0
4
NOTE
Description
0
0
3
0
0
2
COMP
FlexTimer Module (FTMV1)
1
0
COMBINE
0
0
11-21