mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 505

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
ESEQC (W)
CPUSTOP
CSTAT (R)
CPUHALT
CLKSW
29–27
Field
31
30
26
Indicates that the CPU is in the halt state. The CPU state may be running, stopped, or halted, which is determined
by the CPUHALT and CPUSTOP bits as shown below.
Indicates that the CPU is in the stop state. The CPU state may be running, stopped, or halted, which is determined
by the CPUHALT and CPUSTOP bits as shown in the CPUHALT bit description.
During reads, indicates the BDM command status.
000 Command done, no errors
001 Command done, data invalid
01x Command done, illegal
1xx Command busy, overrun
If an overrun is detected (CSTAT = 1xx), the following sequence is suggested to clear the source of the error:
1. Issue a SYNC command to reset the BDC channel.
2. The host issues a BDM NOP command.
3. The host checks the channel status using a READ_XCSR_BYTE command.
4. If XCSR[CSTAT] = 000
During writes, the ESEQC field is used for the erase sequence control during flash programming. ERASE must
also be set for this bit to have an effect.
000 User mass erase
Else Reserved
Note: See the Memory chapter for a detailed description of the algorithm for clearing security.
Select source for serial BDC communication clock.
0 Alternate, asynchronous BDC clock, typically 10 MHz
1 Synchronous bus clock (CPU clock divided by 2)
The initial state of the XCSR[CLKSW] bit is loaded by the hardware in response to certain reset events and the
state of the BKGD pin as described in
then status is okay; proceed
else
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Halt the CPU with a BDM BACKGROUND command
Repeat steps 1,2,3
If XCSR[CSTAT] ≠ 000, then reset device
Table 22-7. XCSR Field Descriptions
[CPUHALT]
XCSR
0
0
1
Figure
[CPUSTOP]
22-2.
XCSR
0
1
0
Description
Running
Stopped
Halted
CPU State
Version 1 ColdFire Debug (CF1_DEBUG)
22-13

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