mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 380

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Multipurpose Clock Generator (MCGV3)
16.4
16.4.1
The MCG operates in one of the modes described in
16-12
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
FLL Bypassed
Internal (FBI)
FLL Bypassed
External (FBE)
Mode
Functional Description
MCG Modes of Operation
The MCG restricts transitions between modes. For the permitted transitions,
see
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 00
• MCGC3[PLLS] = 0
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 00
• MCGC1[RDIV] is programmed
• MCGC3[PLLS] = 0
• MCGC1[IREFS] = 1
• MCGC1[CLKS] = 01
• MCGC2[LP] = 0 (or the BDM is
• MCGC3[PLLS] = 0
• MCGC1[IREFS] = 0
• MCGC1[CLKS] = 10
• MCGC1[RDIV] is programmed
• MCGC2[LP] = 0 (or the BDM is
• MCGC3[PLLS] = 0
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz.
enabled)
to divide the reference clock to
be within the range of 31.2500
to 39.0625 kHz
enabled)
Section 16.4.2, “MCG Mode State Diagram.”
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Related field values
Table 16-11. MCG Modes of Operation
Default. MCGOUT is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to a
multiplication factor, as selected by the DRS[1:0] and DMX32 bits, times
the internal reference frequency. MCGLCLK is derived from the FLL, and
the PLL is disabled in a low-power state.
MCGOUT is derived from the FLL clock, which is controlled by the
external reference clock. The external reference clock that is enabled
can be produced by an external crystal, ceramic resonator, or another
external clock source connected to the required crystal oscillator
(XOSC). The FLL clock frequency locks to a multiplication factor, as
selected by the DRS[1:0] and DMX32 bits, times the external reference
frequency, as specified by MCGC1[RDIV], MCGC2[RANGE], and
MCGC3[DIV32]. MCGLCLK is derived from the FLL, and the PLL is
disabled in a low-power state.
MCGOUT is derived from the internal reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while the MCGOUT clock is driven
from the internal reference clock.
MCGOUT is derived from the internal reference clock. The FLL clock is
controlled by the internal reference clock, and the FLL clock frequency
locks to a multiplication factor, as selected by the DRS[1:0] and DMX32
bits, times the internal reference frequency. MCGLCLK is derived from
the FLL, and the PLL is disabled in a low-power state.
MCGOUT is derived from the external reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
MCGOUT is derived from the external reference clock. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC).The FLL clock is controlled by the
external reference clock, and the FLL clock frequency locks to a
multiplication factor, as selected by the DRS[1:0] and DMX32 bits, times
the external reference frequency, as selected by MCGC1[RDIV],
MCGC2[RANGE], and MCGC3[DIV32]. MCGLCLK is derived from the
FLL, and the PLL is disabled in a low-power state.
NOTE
Table
16-11.
Description
Freescale Semiconductor