mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 498

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Version 1 ColdFire Debug (CF1_DEBUG)
22.2
Table 22-3
visibility bus. A standard 6-pin debug connector is shown in
BDM
22-6
Background Debug
Breakpoint (BKPT)
Processor Status
Processor Status
(DDATA[3:0])
Debug Data
Clock 0 & 1
(PSTCLKn)
Pinout”.
(PST[3:0])
(BKGD)
Signal
External Signal Descriptions
describes the debug module’s 1-pin external signal (BKGD) and the signals associated with the
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Single-wire background debug interface pin. The primary function of this pin is for bidirectional serial
communication of background debug mode commands and data. During reset, this pin selects
between starting in active background (halt) mode or starting the application program. This pin also
requests a timed sync response pulse to allow a host development tool to determine the correct clock
frequency for background debug serial communications.
Input requests a manual breakpoint. Assertion of BKPT puts the processor into a halted state after
the current instruction completes. Halt status is reflected on processor status signals (PST[3:0]) as
the value 0xF. If CSR[BKD] is set (disabling normal BKPT functionality), asserting BKPT generates a
debug interrupt exception in the processor.
Two separate half-speed output signals to externally derive the processor status clock. The PSTCLK0
and PSTCLK1 signals operate at half speed compared to the processor clock with PSTCLK1 delayed
by half a processor clock period relative to PSTCLK0. Externally, these two clock signals should be
exclusive-OR’d together and then complemented (an exclusive-NOR boolean function) to generate a
derived processor status clock suitable for sampling the PST[3:0] and DDATA[3:0] outputs.
Specifically, the rising-edge of the derived processor status clock defines the sample point for
capturing the PST/DDATA outputs.
The state of CSR[VBD] controls the package pin muxing:
See
definition of the PST values.
These output signals display the register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the CSR.
Additionally, execution of the WDDATA instruction by the processor captures operands which are
displayed on DDATA. These signals are updated each processor cycle.
These output signals report the processor status.
These outputs indicate the current status of the processor pipeline and, as a result, are not related to
the current bus transfer. The PST value is updated each processor cycle.
• If CSR[VBD] = 0, the VBus is enabled, the PSTCLKn, PST[3:0] and DDATA[3:0] outputs are
• If CSR[VBD] = 1, the VBus is disabled, the PSTCLKn, PST and DDATA outputs are all quiescent
functional and enabled in the appropriate GPIO logic and BKPT is routed into the debug module.
and the appropriate GPIO logic is disabled. The BKPT pin is logically disconnected from the debug
module.
Figure 22-3
for details on the PSTCLKn behavior and the derived PSTCLK and
Table 22-3. Debug Module Signals
Description
Section 22.4.5, “Freescale-Recommended
Table 22-26
shows the encoding of these signals.
Freescale Semiconductor
Table 22-26
for