mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 59

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

4.4.2.1
The FCDIV register is used to control the length of timed events in program and erase algorithms executed
by the flash memory controller.
All bits in the FCDIV register are readable and writable with restrictions as determined by the value of
FDIVLD when writing to the FCDIV register (see
4.4.2.2
The FOPT register holds all bits associated with the security of the MCU and flash module.
All bits in the FOPT register are readable but are not writable.
The FOPT register is loaded from the flash configuration field (see
sequence, indicated by F in
Freescale Semiconductor
FDIV[5:0]
FDIVLD
PRDIV8
Reset
Reset
Field
5–0
7
6
W
W
R
R
FDIVLD
Clock Divider Load Control — When writing to the FCDIV register for the first time after a reset, the value of
the FDIVLD bit written controls the future ability to write to the FCDIV register:
0 Writing a 0 to FDIVLD locks the FCDIV register contents; all future writes to FCDIV are ignored.
1 Writing a 1 to FDIVLD keeps the FCDIV register writable; next write to FCDIV is allowed.
When reading the FCDIV register, the value of the FDIVLD bit read indicates the following:
0 FCDIV register has not been written to since the last reset.
1 FCDIV register has been written to since the last reset.
Enable Prescalar by 8
0 The bus clock is directly fed into the clock divider
1 The bus clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the bus clock down to a frequency
of 150 kHz–200 kHz. The minimum divide ratio is 2 (PRDIV8 = 0, FDIV = 0x01) and the maximum divide ratio is
512 (PRDIV8 = 1, FDIV = 0x3F). Please refer to
information.
Flash Clock Divider Register (FCDIV)
Flash Options Register (FOPT and NVOPT)
F
0
7
7
KEYEN
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
PRDIV8
0
F
6
6
Figure
Figure 4-3. Flash Clock Divider Register (FCDIV)
Figure 4-4. Flash Options Register (FOPT)
.
4-4.
Table 4-7. FCDIV Field Descriptions
0
0
0
5
5
0
0
0
4
4
Table
Section 4.4.3.1, “Writing the FCDIV Register”
Description
.
4-7).
3
0
3
0
0
FDIV
Section
0
0
0
2
2
4.2.2) during the reset
0
F
1
1
for more
SEC
0
F
Memory
0
0
4-15