mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 483

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow occurs.
21.3.4
TPMxCnSC contains the channel-interrupt-status flag and control bits that configure the interrupt enable,
channel configuration, and pin function.
Freescale Semiconductor
Reset
Reset
CHnIE
CHnF
MSnB
Field
W
W
7
6
5
R
R
CHnF
Channel n flag. When channel n is an input capture channel, this read/write bit is set when an active edge occurs
on the channel n input. When channel n is an output compare or edge-aligned/center-aligned PWM channel,
CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF
is not set even when the value in the TPM counter registers matches the value in the TPM channel n value
registers.
A corresponding interrupt is requested when this bit is set and channel n interrupt is enabled (CHnIE = 1). Clear
CHnF by reading TPMxCnSC while this bit is set and then writing a logic 0 to it. If another interrupt request occurs
before the clearing sequence is completed CHnF remains set. This is done so a CHnF interrupt request is not lost
due to clearing a previous CHnF.
Reset clears this bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n.
1 Input capture or output compare event on channel n.
Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears this bit.
0 Channel n interrupt requests disabled (use for software polling).
1 Channel n interrupt requests enabled.
Mode select B for TPM channel n. When CPWMS is cleared, setting the MSnB bit configures TPM channel n for
edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in
TPM Channel n Status and Control Register (TPMxCnSC)
0
0
0
7
7
Figure 21-11. TPM Channel n Status and Control Register (TPMxCnSC)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
CHnIE
0
0
6
6
Table 21-5. TPMxCnSC Field Descriptions
MSnB
5
0
5
0
MSnA
0
0
4
TPMxMOD[7:0]
4
Description
ELSnB
0
0
3
3
ELSnA
0
0
2
2
Timer/PWM Module (TPMV3)
Table
0
0
0
1
1
21-6.
0
0
0
0
0
21-11