mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 507

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.3.3
The 32-bit CSR2 is partitioned into two sections. The upper byte contains status and configuration bits
always accessible to the BDM interface, even if debug mode is disabled. The lower 24 bits contain fields
related to the configuration of the PST trace buffer (PSTB).
There are multiple ways to reference CSR2. They are summarized in
Freescale Semiconductor
APCENB
APCSC
Field
2–1
0
WRITE_CSR2_BYTE Writes CSR2[31
READ_CSR2_BYTE Reads CSR2[31
READ_DREG
Method
Configuration/Status Register 2 (CSR2)
Automatic PC synchronization control. Determines the periodic interval of PC address captures, if
XCSR[APCENB] is set. When the selected interval is reached, a SYNC_PC command is sent to the ColdFire
CPU. For more information on the SYNC_PC operation, see the APCENB description.
The chosen frequency depends on CSR2[APCDIV16] as shown in the equation and table below:
Automatic PC synchronization enable. Enables the periodic output of the PC which can be used for PST/DDATA
trace synchronization and code profiling.
As described in XCSR[APCSC], when the enabled periodic timer expires, a SYNC_PC command is sent to the
ColdFire CPU which generates a forced instruction fetch of the next instruction. The PST/DDATA module captures
the target address as defined by CSR[9] (two bytes if CSR[9] is cleared, three bytes if CSR[9] is set). This
produces a PST sequence of the PST marker indicating a 2- or 3-byte address, followed by the captured
instruction address.
0 Automatic PC synchronization disabled
1 Automatic PC synchronization enabled
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Reads CSR2[31
Table 22-7. XCSR Field Descriptions (continued)
[APCENB]
XCSR
Table 22-8. CSR2 Reference Summary
PC address capture period
1
1
1
1
1
1
1
1
–
–
–
24] from the BDM interface. Available in all modes.
24] from the BDM interface. Available in all modes.
0] from the BDM interface. Classified as a non-intrusive BDM command.
[APCDIV16]
CSR2
0
0
0
0
1
1
1
1
Description
Reference Details
[APCSC]
=
XCSR
2
--------------------------------------------------------- -
00
01
10
11
00
01
10
11
(
APCSC
16
APCDIV16
+
2048 cycles
4096 cycles
8192 cycles
16384 cycles
128 cycles
256 cycles
512 cycles
1024 cycles
1
)
SYNC_PC Interval
×
Table
1024
Version 1 ColdFire Debug (CF1_DEBUG)
22-8.
Eqn. 22-1
22-15