mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 281

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

12.3.5
In slave mode, the same functions are available after an address match has occurred.
The TX bit in IICC must correctly reflect the desired direction of transfer in master and slave modes for
the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is
desired, reading the IICD does not initiate the receive.
Reading the IICD returns the last byte received while the IIC is configured in master receive or slave
receive modes. The IICD does not reflect every byte transmitted on the IIC bus, nor can software verify
that a byte has been written to the IICD correctly by reading it back.
In master transmit mode, the first byte of data written to IICD following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required
R/W bit (in position bit 0).
12.3.6
Freescale Semiconductor
Reset
Reset
Field
DATA
7–0
W
W
R
R
GCAEN
IIC Data I/O Register (IICD)
IIC Control Register 2 (IICC2)
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
0
0
7
7
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
ADEXT
0
0
6
6
Figure 12-7. IIC Control Register (IICC2)
Figure 12-6. IIC Data I/O Register (IICD)
Table 12-7. IICD Field Descriptions
0
0
0
5
5
NOTE
0
0
0
4
4
Description
DATA
3
0
3
0
0
AD10
0
0
2
2
Inter-Integrated Circuit (IICV2)
AD9
0
0
1
1
AD8
0
0
0
0
12-9