mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 291

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Chapter 13
Interrupt Controller (CF1_INTC)
13.1
The CF1_INTC interrupt controller (CF1_INTC) is intended for use in low-cost microcontroller designs
using the Version 1 (V1) ColdFire processor core. In keeping with the general philosophy for devices based
on this low-end 32-bit processor, the interrupt controller generally supports less programmability
compared to similar modules in other ColdFire microcontrollers and embedded microprocessors.
However, CF1_INTC provides the required functionality with a minimal silicon cost.
These requirements guide the CF1_INTC module definition to support Freescale’s Controller Continuum:
Table 13-1
processing as these differences are important in the definition of the CF1_INTC module. Throughout this
document, the term IRQ refers to an interrupt request and ISR refers to an interrupt service routine to
process an interrupt exception.
Freescale Semiconductor
Core-enforced IRQ Sensitivity No
Non-Maskable IRQ Support
•
•
•
Exception Stack Frame
Exception Vector Table
The priorities of the interrupt requests between comparable HCS08 and V1 ColdFire devices are
identical.
Supports a mode of operation (through software convention with hardware assists) equivalent to
the S08’s interrupt processing with only one level of nesting.
Leverages the current ColdFire interrupt controller programming model and functionality, but with
a minimal hardware implementation and cost.
More on Vectors
Interrupt Levels
INTC Vectoring
Introduction
Attribute
provides a high-level architectural comparison between HCS08 and ColdFire exception
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
32 two-byte entries, fixed location at upper
end of memory
2 for CPU + 30 for IRQs, reset at upper
address
5-byte frame: CCR, A, X, PC
1 = f(CCR[I])
No
Fixed priorities and vector assignments
Table 13-1. Exception Processing Comparison
HCS08
113 four-byte entries, located at lower end of
memory at reset, relocatable with the VBR
64 for CPU + 40 for IRQs, reset at lowest
address
8-byte frame: F/V, SR, PC; General-purpose
registers (An, Dn) must be saved/restored
by the ISR
7= f (SR[I]) with automatic hardware support
for nesting
Yes, with level 7 interrupts
Level 7 is edge sensitive, else level sensitive
Fixed priorities and vector assignments, plus
any 2 IRQs can be remapped as the highest
priority level 6 requests
V1 ColdFire
13-1