mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 499

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.3
In addition to the BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains a number of registers. Most of these registers (all except the
PST/DDATA trace buffer) are also accessible (write-only) from the processor’s supervisor programming
model by executing the WDEBUG instruction. Thus, the breakpoint hardware in the debug module can be
read (certain registers) or written by the external development system using the serial debug interface or
written by the operating system running on the processor core. Software is responsible for guaranteeing
that accesses to these resources are serialized and logically consistent. The hardware provides a locking
mechanism in the CSR to allow the external development system to disable any attempted writes by the
processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued during the
processor’s execution of the WDEBUG instruction to configure debug module registers or the resulting
behavior is undefined.
These registers, shown in
implemented bits and unimplemented bits are reserved and must be cleared. These registers are also
accessed through the BDM port by the commands, WRITE_DREG and READ_DREG, described in
Section 22.4.1.5, “BDM Command Set
specifies the register, as shown in
Freescale Semiconductor
Memory Map/Register Definition
~(PSTCLK0 ^ PSTCLK1)
CF1Core VBus Signals
VBus Output Signals
PST, DDATA Pins
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
PSTCLK0 Pin
PSTCLK1 Pin
PST, DDATA
CPU_CLK
PSTCLK0
PSTCLK1
Table
22-4, are treated as 32-bit quantities regardless of the number of
Table
Figure 22-3. Deriving PSTCLK
1
Summary.” These commands contain a 5-bit field, DRc, that
22-4.
2
3
Version 1 ColdFire Debug (CF1_DEBUG)
4
22-7