mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 389

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
2. Then, FBE must transition either directly to PBE mode or first through BLPE mode and then to
3. Lastly, PBE mode transitions into PEE mode:
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
c) Because RANGE = 1, set DIV32 (bit 4) in MCGC3 to allow access to the proper RDIV bits
d) MCGC1 = 0x98 (%10011000)
e) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
f) Loop until CLKST (bits 3 and 2) in MCGSC is %10, indicating that the external reference
PBE mode:
a) BLPE: If a transition through BLPE mode is desired, first set LP (bit 3) in MCGC2 to 1.
b) BLPE/PBE: MCGC3 = 0x58 (%01011000)
c) BLPE: If transitioning through BLPE mode, clear LP (bit 3) in MCGC2 to 0 here to switch to
d) PBE: Loop until PLLST (bit 5) in MCGSC is set, indicating that the current source for the
e) PBE: Then loop until LOCK (bit 6) in MCGSC is set, indicating that the PLL has acquired lock
a) MCGC1 = 0x18 (%00011000)
has been initialized.
while in an FLL external mode.
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
– RDIV (bits 5-3) set to %011, or divide-by-256 because 8MHz / 256 = 31.25 kHz which is
– IREFS (bit 2) cleared to 0, selecting the external reference clock
source for the reference clock
clock is selected to feed MCGOUT
– PLLS (bit 6) set to 1, selects the PLL. At this time, with an RDIV value of %011, the FLL
– DIV32 (bit 4) still set at 1. Because the MCG is in a PLL mode, the DIV32 bit is ignored.
– VDIV (bits 3-0) set to %1000, or multiply-by-32 because 1 MHz reference * 32= 32MHz.
PBE mode
PLLS clock is the PLL
– CLKS (bits7 and 6) in MCGSC1 set to %00 in order to select the output of the PLL as the
source
in the 31.25 kHz to 39.0625 kHz range required by the FLL
reference divider of 256 is switched to the PLL reference divider of 8 (see
resulting in a reference frequency of 8 MHz/ 8 = 1 MHz. In BLPE mode,changing the PLLS
bit only prepares the MCG for PLL usage in PBE mode
Keeping it set at 1 makes transitions back into an FLL external mode easier.
In BLPE mode, the configuration of the VDIV bits does not matter because the PLL is
disabled. Changing them only sets up the multiply value for PLL usage in PBE mode
system clock source
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Multipurpose Clock Generator (MCGV3)
Table
16-3),
16-21