mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 35

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

2.1.7
The active-low RESET pin provides the mechanism for off-chip logic to reset the microcontroller. After a
power-on reset (POR), RESET is configured:
In this configuration, after a reset, the internal pullup resistor pulls RESET high unless one of the following
conditions is true:
2.1.8
The IRQ pin is the input source for the IRQ interrupt. If the IRQ function is not enabled, this pin can be
used for TPMCLK. In EMC-sensitive applications, an external RC filter is recommended on the IRQ pin.
See
2.1.9
During a power-on-reset (POR) or background debug force reset (see bit ENBDM in
“Extended Configuration/Status Register (XCSR),”
as a mode select pin. Immediately after any reset, the pin functions as the background pin and can be used
for background debug communication.
The BKGD/MS pin has an internal pullup device that is always enabled. If this pin is unconnected, the
microcontroller will enter normal operating mode at the rising edge of the internal reset after a POR or
forced BDC reset. If a debug system is connected to the 6-pin standard background debug header, it can
hold BKGD/MS low during a POR or immediately after issuing a background debug force reset
forces the microcontroller to halt mode.
The BKGD/MS pin is used primarily for background debug controller (BDC) communications using a
custom protocol that uses 16 clock cycles of the target microcontroller’s BDC clock per bit time. The target
microcontroller’s BDC clock could be as fast as the bus clock rate, so there must never be any significant
capacitance connected to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speed-up pulses to ensure fast rise times. Small capacitances from
1. Specifically, BKGD must be held low through the first 16 bus cycles after deassertion of the internal reset.
Freescale Semiconductor
•
•
•
•
Figure 2-3
As an open drain to indicate whether an internal reset (caused by an on-chip mechanism) is in
progress
With its internal pullup resistor enabled
Off-chip logic is asserting RESET.
An internal reset is in progress. (A reset takes approximately n CPU cycles.)
RESET
IRQ/TPMCLK
Background / Mode Select (BKGD/MS)
•
•
for an example.
The RESET pin does not have a clamp diode to V
driven above V
In EMC-sensitive applications, an external RC filter is recommended on
the RESET pin. See
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
DD
.
Figure 2-3
NOTE
for an example.
for more information), the BKGD/MS pin functions
DD
and must not be
Section 22.3.2,
Pins and Connections
1
, which
2-9