mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 323

no-image

mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf51ac256aCFGE
Manufacturer:
FREESCALE
Quantity:
2 400
Part Number:
mcf51ac256aCFGE
Manufacturer:
FREESCALE
Quantity:
2 400
Part Number:
mcf51ac256aCFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf51ac256aCLKE
Manufacturer:
FREESCALE
Quantity:
1 500
Part Number:
mcf51ac256aCLKE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf51ac256aCPUE
Manufacturer:
MURATA
Quantity:
1 000
15.3.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
SJW[1:0]
BRP[5:0]
SLPAK
INITAK
Field
Field
7:6
5:0
1
0
Reset:
W
R
MSCAN Bus Timing Register 0 (CANBTR0)
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 15.5.5.4, “MSCAN Sleep
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.CPU clearing the SLPRQ bit will also reset
the SLPAK bit.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN is in initialization mode
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
SJW1
Section 15.5.5.5, “MSCAN Initialization
Table
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
SJW1
15-5).
0
0
1
1
Table 15-2. CANCTL1 Register Field Descriptions (continued)
Table
Figure 15-5. MSCAN Bus Timing Register 0 (CANBTR0)
Table 15-4. Synchronization Jump Width
SJW0
Table 15-3. CANBTR0 Register Field Descriptions
6
0
15-4).
BRP5
0
Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
5
SJW0
0
1
0
1
Mode”). It is used as a handshake flag for the INITRQ initialization
BRP4
4
0
Description
Description
BRP3
Synchronization Jump Width
0
3
Freescale’s Controller Area Network (MSCANV1)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP2
2
0
BRP1
0
1
BRP0
0
0
15-7

Related parts for mcf51ac256a