MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 99

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
15.0 JTAG (Joint Test Action Group) Operation
The MT9072 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-
1990. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). Figure 10
shows the BST architecture which is made up of the following four basic elements. See Figure 70 for JTAG
timing.
1. Test Access Port (TAP)
2. TAP Controller
3. Instruction Register (IR)
4. Test Data Registers (TDR)
Address Bit Name Address Bit Name
Y70-Y8F
Status Register or
Real Time Source
PCM30
PCM30
PCM30
PCM30
PCM30
PCM30
PCM30
PCM30
PCM30
PCM30
Y11
Y11
Y11
PCM30
ABCD
Sa5-8
Sa5-8
CALN
Sa5
Sa6
Sa6
Sa6
Sa6
Sa6
Sa6
Sa5
T2
T1
Table 52 - Interrupt Source & Status Register Summary (E1)
Interrupt Status
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Y36
Register
ONESECI
Sa6N8I
Sa6V3I
Sa6V2I
Sa6V1I
Sa6V0I
CASRI
CALNI
Sa5VI
Sa6NI
Sa5TI
SaNI
SaTI
T2I
T1I
O
N
A
N
A
T
L
I
Sa6 bit 3 value was one when Sa6N8 toggled from zero to one
Sa6 bit 2 value was one when Sa6N8 toggled from zero to one
Sa6 bit 1 value was one when Sa6N8 toggled from zero to one
Sa6 bit 0 value was one when Sa6N8 toggled from zero to one
Sa5 bit value was one when Sa6N8 toggled from zero to one
CRC-4 100ms timer toggled from zero to one
sequence of 8 identical Sa6 nibbles occurred
CRC-4 10ms timer toggled from zero to one
receive CAS bit (ABCD) changed
1s timer toggled from zero to one
Sa5,6,7 or 8 nibble changed
Sa5,6,7 or 8 bits changed
CRC-4 2ms timer toggled
Interrupt Description
Sa6 nibble changed
Sa5 bit changed
MT9072
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