MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 190

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
190
Table 174 - Sync, CRC-4 Remote, Alarms, MAS and Phase Latched Status Register (Address Y24)
Bit
10
11
9
8
7
6
5
4
3
2
1
0
MSYNCL Receive Multiframe Alignment Latch. When the MSYNC status bit (register address Y10)
CSYNCL Receive CRC-4 Synchronization Latch. When the CSYNC status bit (register address Y10)
RCRC0L Remote CRC-4 and RAI T10 Latch. When the RCRC0 status bit (register address Y10)
RCRC1L Remote CRC-4 and RAI T450 Latch. When the RCRC1 status bit (register address Y10)
BSYNCL Receive Basic Frame Alignment Latch. When the BSYNC status bit (register address Y10)
AUXPL
AIS16L
RFAILL
LOSSL
CEFSL
Name
RAIL
AISL
Auxiliary Pattern Latch. When the AUXP status bit (register address Y12) toggles from zero
to one, this status bit is latched to one. This bit is cleared when either this register, or the
interrupt status register (register address Y34) is read.
Remote Alarm Indication Status Latch. When the RAI (A) status bit (register address Y12
and Y13) toggles from zero to one, or from one to zero, this status bit is latched to one. This
bit is cleared when either this register, or the interrupt status register (register address Y34) is
read.
Alarm Indication Status Signal Latch. When the AIS status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
Alarm Indication Signal 16 Status Latch. When the AIS16 status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
Loss of Signal Status Indication Latch. When the LOSS status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
toggles from zero to one, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
toggles from zero to one, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
Consecutively Errored Frame Alignment Signal Latch. When the CEFS status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y34) is read.
Remote CRC-4 Multiframe Generator/Detector Failure Latch. When the status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y34) is read.
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
Functional Description
(E1)
Advance Information