MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 195

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Bit
15
14
13
12
10
Bit
11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Table 181 - Frame Alignment Signal (FAS) Error Count Latch (R/W Address Y2B) (E1)
Name
BEL7
BEL6
BEL5
BEL4
BEL3
BEL2
BEL1
BEL0
FEL7
FEL6
FEL5
FEL4
FEL3
FEL2
FEL1
FEL0
CEL15
CEL14
CEL13
CEL12
CEL11
CEL10
Name
CEL9
CEL8
CEL7
CEL6
CEL5
CEL4
CEL3
CEL2
CEL1
CEL0
Table 180 - CRC-4 Error Count Latch (R/W Address Y2A) (E1)
Frame Alignment Signal (FAS) Bit Error Count Latch. These bits make up a latch which
samples the current value of the Frame Alignment Signal (FAS) Bit Error Counter (upper
byte of address Y1A) on the rising edge of the internal one second timer (ONESEC
register address Y11). This latch is cleared with a RESET (RESET pin or RST bit). BEL0 is
the least significant bit (LSB).
Frame Alignment Signal (FAS) Error Count Latch. These bits make up a latch which
samples the current value of the Frame Alignment Signal (FAS) Error Counter (lower byte
of address Y1A) on the rising edge of the internal one second timer (ONESEC register
address Y11). This latch is cleared with a RESET (RESET pin or RST bit). FEL0 is the
least significant bit (LSB).
CRC-4 Error Count Latch. These bits make up a latch which samples the current value
of the CRC-4 Error Counter (address Y19) on the rising edge of the internal one second
timer (ONESEC register address Y11). This latch is cleared with a RESET (RESET pin
or RST bit). CEL0 is the least significant bit (LSB).
Functional Description
Functional Description
MT9072
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