MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 57

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
6.1.1
When EDLEN(Y06) is set to "1" the data link (DL) bits can be sourced/sinked to and from the TxDL and RxDL
pins, by enabling the corresponding pulses in either gapped clocks or enable low signals provided at the
RxDLC and TxDLC pins. The option of either gapped clock or enable signal is selected by control bit DLCK
(Register address Y06).
In D4 or ESF mode, the optional serial data link operates at 4 khz. In D4 mode the data link pins are used to
send/receive Fs bits only, while the Ft bits are generated internally. See Figures 40 to 43.
6.1.1.1 T1 Data Link (DL) Pin Data Received from PCM24
The RxDLC clock is derived from the receive extracted clock (EXCLi).The B8ZS decoded receive data, at
1.544Mbit/s, is clocked out of the device on the RxDL pin with the rising edge of EXCLi and is aligned to
RXDLC. In order to facilitate the attachment of this data stream to a Data Link controller, the clock signal
RxDLC (falling edge of EXCLi) consists of positive pulses, of nominal width of 344 ns, during the Fs bit cell
times that are selected for the Data Link, with the rising edge aligned with the middle of the bit cell. DL data will
not be lost or repeated when a receive frame slip occurs as the DL data does not pass through the elastic
buffer. See Figures 42 to 43 for timing requirements.
6.1.1.2 T1 Data Link (DL) Pin Data Sent to PCM24
The TxDLC clock is derived from the transmit clock (TXCL) and is provided one frame before its usage on the
appropriate S-bit. Hence the TXDLC clock is provided one frame before it is used in ESF Mode in Frames 2, 4,
6, 8, 10, 12, 14, 16, 18, 20, 22, 24. See Figures 40 to 41 for timing requirements
6.2
Table 12 shows the contents of the transmit and receive Frame Alignment Signals (FAS) and Non-frame
Alignment Signals (NFAS) of timeslot zero of a PCM30 signal. Even numbered frames (CRC Frame # 0, 2,
4,...) are FASs and odd numbered frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits of each channel are
numbered 1 to 8, with bit 1 being the most significant and bit 8 the least significant. The Data Link (DL) bits,
also referred to as National bits, are the Sa4, Sa5, Sa6, Sa7 and Sa8 bits of the PCM30 timeslot zero NFAS
frames. Any number and combination of these bits may be used for the transport of maintenance and
performance monitoring information across the PCM30 link. The DataLink in controlled by the address Y06 and
Y08.
The received Data Link bits are always sent to the DataLink Pins and the National bit buffers(YC0-YC4)
The Data Link (DL) bits (S
the following four ways:
•
•
•
•
Note: that the user can source different Sa bits from a combination of the above 4 methods. For instance the
Sa
address YB1 to YB4).
The registers related to the configuration control and status of the data link are shown in Table 17.
4
External serial port pins. Hence the user can use pins (TxDL and TxDLC) for transmit data link access
and RxDL and RXDLC for receive data link access.
receiver Receive 5 bit register (RNU4-8 address YC0-YC4).
ST-BUS access Transmit ST-BUS (DSTi timeslot 0) enabled by transparent mode.
On board HDLC for Timeslot 0.
Micro port access which would use Transmit 5 bit register (TNU4-8 address YB0 to YB4). For the
bit could be sourced from the External Serial Port and Sa
E1 Data Link (DL) Operation
T1 Data Link (DL) Pin Access
a4
~S
a8
) of the PCM30 timeslot zero NFAS frames can be accessed by the MT9072 in
5
to Sa
8
from the micro port register (TNU5-8
MT9072
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